Method for camera shutter timing

ABSTRACT

A system for timing photographic shutters, functions related thereto (i.e. sync advance or delay), or any occurrence that can be translated into a pulse of light within the timing range of the system. The system includes activating the camera shutter so that a pulse of light passes therethrough, sensing the duration of the light as it passes between the half-open and half-closed positions of the shutter; generating a plurality of electrical clock pulses during the time between half-open and half-closed positions of the shutter; counting said electrical clock pulses generated; and displaying shutter speed as a function of counted pulses.

United States Patent Lawrence A. Westhaver [72] inventor 13001 Old Stagecoach Road, Laurel, Md. 20810 [21] Appl. No. 865,391 [22] Filed Oct. 10,1969 [45] Patented Sept. 7, 1971 [54] METHOD FOR CAMERA SHUTTER TIMING 9 Claims, 2 Drawing Figs.

[52] U.S.Cl 73/5 [51] Int. Cl ..G03h 43/02, G041 1 1/08 [50] Field of Search. 73/5; 250/214 P, 229; 346/108 [56] References Cited UNITED STATES PA'lliN'lS 2.261.010 10/1941 Weiss 73/5 X 2,477,578 8/1949 Coleman 73/5 Primary ExaminerLouis R. Prince Assistant Examiner-William A. Henry, II

Att0meyDavid I-l. Semmes ABSTRACT: A system for timing photographic shutters, functions related thereto (Le. sync advance or delay), or any occurrcnce that can be translated into a pulse of light within the timing range of the system.

The system includes activating the camera shutter so that a pulse of light passes therethrough, sensing the duration of the light as it passes between the hall open and half-closed positions of the shutter; generating a plurality of electrical clock pulses during the time between half-open and half-closed posi tions of the shutter; counting said electrical clock pulses generated; and displaying shutter speed as a function of counted pulses.

METHOD FOR CAMERA SHUTTER TIMING BACKGROUND OF THE INVENTION 1. Field of the Invention Conventional cameras contain a broad and selective range of shutter speeds, enabling the photographer to adjust the shutter speed, as desired. Presumably, the shutter operates at the selected speed. However, as a practical matter, very little attention has been given to measuring the shutter speed to determine if the actual speed of the shutter is equivalent to the calibration presented for the selected speed. Experience indicates that, more often than not, there are wide discrepancies between the calibrated speed and the actual speed obtained. Experience indicates, furthermore, that, for speeds in excess of one-hundredth of a second the amount of error may exceed 50 percent.

The present invention is directed to providing a method for accurately and conveniently measuring shutter speed. As a result, the camera manufacturer, as well as the photographer, can be provided with accurate knowledge as to the actual shutter speed obtained in a given camera. The method is extended to measuring, also, the number of frames per second obtained in a motion picture camera.

2. Description of the Prior Art Prior art searching has developed the following prior art:

Abell 2,602,324

Richard 3,046,555

Goldfarb 3,229,497

Handbook of INdustrial Electronic Control Circuits (by Markus and Zeluff, McGraw-Hill 1956 page 195 These references show that a good deal of attention has been directed to shutter timing. However, the apparatus for testing is relatively complex and is circuit dependent to the extent that variations or load in the testing circuit may influence the detected timing of the shutter. Also, the devices are not, for the most part, adaptable to repetitive testing in a workshop situation, such that the tested shutter can be adjusted, thence repetitively tested. Furthermore, none of the devices enables the accurate measurement or timing of the shutter from the half-open to the half-closed position, as is inherent in the present method.

SUMMARY OF THE INVENTION A photosensitive field-effect transistor, in a source follower configuration, senses a pulw of light passed by the shutter of a camera under test. With one setup adjustment, the sensor and associated circuitry will produce an electrical pulse the duration of which is equal to the time between the half-open and the half-closed conditions of the shutter. This is the effective period of the shutter.

Two storage flip-flops with an exclusive or gate form a logic circuit capable of producing an electrical pulse the duration of which is equal to the time interval between two events (shutter opening and synch switch closing or vice versa).

Measurement of the duration of either of the aforementiooed pulses is accomplished by using the pulse to enable the s of clock pulses through an electronic gate and counting the number of pulses passed with a counter.

Depending upon the expected length of the pulse, an appropriate clock pulse rate is selected. The fundamental output of a crystal-controlled oscillator is successively divided in tenths by a series of decade counters. This provides a selection of clock pulse rates.

An extension of the same timing chain provides a timing capability for determining the average frames/second rate of a motion picture camera over a several second interval.

A digital readout is provided for the test result contained in the final counter.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 11 is a perspective view of a proposed shutter timer device, constructed according to the present invention, having a light source positioned at the top and a mandrel for supporting a camera adjacent a photosensing element in the bottom; with various diffuser elements being shown in an explosive view; and

FIG. 2 is a circuit diagram of a proposed circuit for timing a shutter according the present method.

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows one device found suitable for practicing the method and comprises a base casing, the upper wall of which supports a mandrel 116 overlying the photosensitive field effect transistor 1 of FIG. 2. The mandrel may receive a diffuser 102 and 104. Shrouds I06, I08, 110, 112 and 114 are used to exclude extraneous light from a diffuser. The base casing contains components associated with the phototransistor as will be described with reference to FIG. 2.

Supported above the base casing is a second casing carrying light and containing various components associated with the numerical readout (tubes 59, 60, and 61) as will also be described with reference to FIG. 2.

In FIG. 2 photosensitive field effect transistor 1 is connected in a source follower configuration. Potentiometer 3 together with resistor 4 form the source load (Rs). Zenor diode 5 serves only to decrease the voltage on the drain of the transistor. Variable resistor 2, the gate resistance (Rg), is connected in a bootstrap configuration to the wiper of Potentiometer 3.

The source follower configuration exhibits a voltage gain less than unity. Therefore the input capacitance is at a minimum being comprised of the drain to gate capacitance (C in parallel with the effective gate to source capacitance (C effective C (IAv), when Av is the voltage gain of the stage). Reduction of the input capacitance is very important since the ability of the circuit to track a pulse of light is limited by the RC time constant of the input. The effective input resistance of the circuit will be R (the setting of resistor 2) multiplied by a factor based on the setting of potentiometer in the absence of light, neglecting an infinitesimal leakage current, there will be no voltage drop across resistor 2. Potentiometer 3 should be adjusted for a circuit output voltage at some arbitrary negative level. This will be indicated on zerocenter voltmeter 7. Resistor 6 prevents overload of meter 7. When light is fully admitted to the transistor 1, as would be the case during the full opening of a shutter under test, a leakage current proportional to the light flows in the gate (I This current flowing through the effective input resistance produces a voltage drop which forces the output of the circuit to rise to a more positive voltage level. By adjustment of resistor 2 the voltage level may be made equal in magnitude to the negative voltage level and positive with respect to ground. Voltmeter 7 facilitates this adjustment.

With the completion of the aforementioned adjustment, when the shutter under test is operated a trapezoidal pulse will be generated. The midpoint of the rise and the midpoint of the fall of the pulse will be at zero volts. The rise and fall times of the pulse correspond to the opening and closing times of the shutter respectively.

Operational amplifier 9, connected as a Schmidt trigger, receives the output of the source follower at its inverting input. Resistors I0 and 11 form a regenerative feedback loop from the output of the amplifier to the noninverting input of the amplifier. The hysteresis of the Schmidt trigger is determined by the ratio of resistor 10 to resistor 11 Le. hysteresis C outpcak Ri llRlO+Rl l where C outpeak is the maximum voltage that the output can swing away from zero. If the hysteresis is made small (Rl0 Rl I) then the input positive and negative switching points will be near zero.

With a trapezoidal pulse at the inverting input of opera tional amplifier 9 the output ofthe amplifier will be a pulse the duration of which will be equal to the time between the halfopen and the half-closed conditions during a shutter operation.

Since the output of the operational amplifier swings both positive and negative and the logic circuits accept only a zero to positive input. resistor 12 and diode 13 are connected as an intermediate clipper to eliminate the negative excursion. Variable resistor 8 is used only to initially balance the amplifier and once set need not be readjusted.

Single-pole-double-throw pushbutton switch 22 is the reset means enabling the operator to initialize the circuitry before making a test. It is shown in the unactivated state. Gate 16 and gate 17 are cross coupled to form a set-reset flip-flop. This flip-flop removes the switch-contact-bounce noise when the reset pushbutton switch 22 is operated. When reset pushbutton 22 is operated the output of gate 16 goes to zero" and the output of gate 17 goes to a one." Upon release of the reset the output of gate 16 returns to a one and gate 17 returns to a zero." Resistors 18 an 19 return the gate inputs to ground whenever the inputs are not being held at a one by the switches.

Gates l4 and are cross coupled to form a set-reset flipflop. A reset connection is provided from the output of gate 17 to an input of gate 15. The flip-flop is initialized by operation of reset 22 which stores a zero" at the output of gate 15 and a one at the output of gate 14. The inputs capable of setting the flip-flop originate at the output of gate (an inverter controlled by the shutter circuitry) and the output of inverter 25 (an inverter controlled by the closing of the synch switch contacts). In any test performed with this instrument a pulse contacts). be generated by the shutter circuitry. This pulse may be followed by or preceded by a pulse originating at the sync switch contacts. Upon the rise of either the shutter" pulse or the synch" pulse, the flip-flop will be set (the output of gate 14 will be zero and the output of gate 15 will be one). The setting of this flip-flop, hereinafter referred to as the initiate timing" flip-flop, hereinafter referred to as the initiate timing" flip-flop, enables the clocking circuitry through buffer inverters 38 and 39.

Buffer inverter 39 drives the reset inputs of BCD (binarycoded decimal) counters 44, 45. 46 and gate 50. The reset inputs of BCD counters 41, 42 and 43 are driven by buffer inverter 38. Under control of the same input, the outputs of 38 and 39 are logically the same. The limited load driving ability (fan-out) of the buffer, inverter circuit made necessary the division of the reset loads between two buffer inverters.

Prior to a test, the outputs of buffer inverters 38 and 39 are at a "one" which holds the BCD counters 41, 42 43, 44, 45 and 46 in a reset condition. Through an input to gate 50, buffer inverter 39 also holds reset a flip-flop consisting of gates 49 and S0.

Initialization, by operation of reset 22, produces a zero at the output of gate 16 which is applied to the inputs of buffer inverters 51 and 52. The output of buffer inverter 52, which is at a one" state, resets BCD counters 54 and 55 and, through an input to gate 65 resets a flip-flop comprised of gates 65 and 66. BCD counter 53, a flip-flop consisting of gates and 31 and a flip-flop consisting of gates 28 and 29 are reset by the output of buffer inverter 51. Again, the outputs of buffer inverters 51 and 52 are logically the same and circuit fan-out dictates the use of two circuits.

Upon release of reset 22, the outputs of buffer inverters 51 and 52 return to a zero state. All circuits are thus reset and ready for initiation of a test.

itiate flip-flop sets, indicating the start of a test the outputs of buffer inverter 38 and 39 return to a zero" state enabling normal counter action in BCD counters 41 42. 43. 44, 45 and 46. The Z8 output of each B('D counter is connected to the input of the succeeding counter providing six successive divi sions by l0 of the input pulse repetition rate. The pulse repetition rates of the Z8 outputs of counters 41. 42 and 43 are l'O kpps., l kpps. and IOC pps. respectively These output signals are selectable at positions C. B and A of switch 37 providing timing in increments of lOOuS l 10" sec 1 ms. l0 sec and 1 cs. (10' sec.) respectively Further division of the pulse repetition rate is accomplished by BCD counters 44, 45 and 46. The cycle time of the outputs being O.l sec., l sec. and l0 sec. respectively.

When in the reset state the Z8 output of counter 46 is at a one" condition. This does not affect the input of gate 49, the static voltage level being blocked by capacitor 47. With resistor 48 returning one input of gate 49 to a zero and the output of gate 50 holding the other input at zero," the output of gate 49 is at a one condition The outputs of gates 49 an 50, cross coupled forming a set-reset flip-flop, will remain sta ble when the output of buffer inverter 39 switches from a one to a zero state When the outputs of buffer inverters 38 and 39 switch from a one to a zero" counting action is started in the chain of BCD counters and the flip-flop comprised of gates 49 and 50 is no longer held in a reset condition As previously noted, BCD counter 46 has a cycle period of IO seconds and in the reset condition the Z8 output is at a one. During the cycle period of l0 seconds, the Z8 output will fall to a zero." This transition is differentiated by capacitor 47 and resistor 48 producing a negative voltage spike at the input of gate 49. Since a positive voltage is required to set the flipflop it will remain in the reset condition. At the end of IO seconds the Z8 output of BCD counter 46 will switch again to a one." Again the transition is differentiated, this time producing a positive voltage spike at the input of gate 49 which sets the flip-flop The setting of the flip-flop, comprised of gates 49 and 50 hereinafter referred to as the IO-second flag," occurs 10 seconds after the setting of the timing initiate" flip-flopv Discounting the small error in the frequency of crystal-controlled oscillator 40, the only error in the length of the 10 second period will he an uncertainty of 1011.3 the length of one cycle of the crystal-controlled oscillator i in starting plus the propagation time through the six BCD counter stages and lO-second flag" flip-flop (typically a total delay of less than 2,usec.).

Inverter 21 drives the line which transmits the shutter pul' se" from the lower housing to the upper housing. lnverter 26 acts as a receiver of the signal The output of inverter 26 ex cept for a very minute time delay will be the same as the out put ofinverter 20 (due to double inversion) Electrical receptacle 23 i a mean of connecting via a cable the sync switch contacts in the shutter under test to the logic circuitry Load resistor 24 returns the input to inverter 25 to a one" condition when the contacts are open. When the sync contacts close the input to inverter 25 is grounded, a zero' condition. The output of inverter 25 will then be a one which will set, through an input to gat. 14, the timing in itiate flip-flop, and. thru an input to gate 28. a flip-flop con sisting of gates 28 an 29 Gates 28 and 29 are the sync flipflop.

In like manner when the shutter under test 15 operated. the shutter pulse at the output of gate 26 will, through an input to gate 30, set a flip-flop consisting 0t gates 30 and 31 Gates 30 and 31 form the shutter" flip-flop The reset output of the sync flip-flop (output of gate 28') is applied to one input to gate 32. The set output of the syno' flip-flop (output of gate 29) is applied to one input of gate 33 Similarly, the reset output of the shutter flip-flop (output of gate 30) is applied to the other input of gate 33 and the set output (output of gate 31 is applied to the other input to gate 32. The outputs ofgates 32 and 33 form the inputs to gate 34.

In Boolean notation the output of gate 32 may be written;

uut sync shutter=sync-shutter The output of gate 33 may be written:

39? shatter. The output of gate 34 may be written:

3, .=i rrX i9.-.@iF shatter From the equation for the output of gate 34 it is apparent that the output is at a one prior to a test (when shutter" and sync" flip-flops are reset) and that the output will be at a zero" only during the interval between the opening of the shutter (setting of shutter flip-flop) and the closing of the sync contacts (setting of sync flip-flop) or vice versa. The output then of gate 34 will be a pulse, at the zero condition, the length of which is equal to the absolute time difference between the occurrence of the two events. This pulse is selectable at position b of switch 35.

inverter 27 provides a pulse, at the zero" condition, the length and timing of which is the same as the -shutter" pulse. This pulse is selectable at position a of a switch 35.

Determination of the duration of either the sync interval pulse or the shutter pulse is accomplished by gating an appropriate clock signal from the wiper of switch 37 (positions a b, c or c d) with the selected pulse at the inputs of gate 36. Gate 36 will allow the clock signal to propagate through to the input of BCD counter 53 only when enabled by the presence of the pulse to be measured.

BCD counters 53, 54 and 55 count the clock pulses propagated during a test to a maximum capacity of 999 counts. if that count is exceeded the flip-flop consisting gates 65 and 66 will fall to a zero" state shutting off base current to transistor 68 through current-limiting resistor 67. This switches transistor 68 from saturation to cutoff and the collector potential will rise to the ionization potential of neon-indicator 69, lighting it. Resistor 70 serves to limit the current through indicator 69. If indicator 69 (the overflow" indicator) lights in the course of a test, the test should be repeated using a slower clockpulse rate.

Decoder drivers 56, 57 and 58 serve to decode the BCD outputs and to drive the appropriate cathode in the gas-filleddecimal-numeric readout tubes. Resistors 62, 63 and 64 serve to limit the current through their readout tubes 59, 60 and 61 respectively.

With switch 35 in position a and switch 37 in position 2 the instrument can count the number of shutter pulses occurring in a lO-second period (useful for checking motion picture cameras). Once reset, the instrument waits for the first shutter pulse. When it occurs, it sets the timing initiate flip-flop which enables the BCD counter-timing chain. The output of gate 50 of the lOsecond flag flip-flop, at a zero, enables the propagation of the shutter pulses through gate 36 to BCD counter 53 until the flip-flop sets at the end of the seconds.

Position f of switch 37 is provided to enable the counting of shutter pulses without time limit.

Iclaim:

l. A method for measuring shutter speed in a camera comprising:

A. supporting the camera shutter adjacent a light source;

B. Activating said shutter, so that a pulse of light passes therethrough;

C. sensing the duration of the light, as it passes between the half-open and half-closed positions of the shutter;

D. generating a plurality of electrical clock pulses during the time between the half-open and half-closed positions of the shutter;

E. counting said electrical clock pulses generated; and

F. displaying speed as a function of counted pulses.

2. A method for measuring shutter speed in a camera comprising:

A. supporting the camera shutter adjacent a light source;

B. activating said shutter, so that a pulse of light passes therethrough;

C. sensing the duration of the pulse of light, as it passes between the half-open and half-closed positions of the shutter; D. generating an electrical pulse equal in duration to the F. measuring shutter speed as a function of said clock-timing pulses.

3. A method for measuring shutter speed in a camera comprising:

A. supporting the camera shutter adjacent a light source;

B. activating said shutter, so that a pulse of light passes therethrough;

C. sensing the duration of the pulse of light, as it passes between the half-open and half-closed positions of the shutter;

D. generating an electrical pulse equal in duration to the pulse of light between the half-open and half-closed positions of the shutter;

E. gating said pulse with a source of clock-timing pulses;

F. measuring shutter speed as a function of said clock-timing pulses; and

G. displaying said shutter speed as a digital readout.

4. Method of measuring shutter speed as in claim 3, including:

H. selectively varying the clock-timing rate, according to the anticipated length of the electrical pulse.

5. Method for measuring shutter speed as in claim 4, including generating of said electrical pulse, such that said pulse swings between a negative voltage and a positive voltage of equal magnitude and has zero voltage at the half-open position of the shutter and zero voltage at the half-closed position of the shutter.

6. Method of measuring shutter speed as in claim 5, wherein said clock-timing pulse rates are an integer power of 10.

7. Method of measuring shutter speed as in claim 6, including displaying overflow when the number of counted timing pulses exceeds the capacity of the counter.

8. Method of measuring frames per second in a motion picture camera, comprising:

A. positioning a light source in the camera film gate;

B. operating the camera for a period of a least 10 seconds;

C. sensing the pulses of light passing through the shutter during the period of operation;

D. initiating a lO-second timing cycle upon the receipt of said first pulse;

E. generating electrical pulses equal in number to the pulses of light;

F. gating said electrical pulses with the 10-second cycle;

G. counting said electrical pulses during said IO-second cycle; and

H. displaying frames per second rate of the camera as a function of counted pulses.

9. Method of measuring absolute time interval between shutter opening and synch contacts closure in cameras comprising:

A. supporting the camera shutter adjacent a light source;

B. activating said shutter so that a pulse of light passes through the shutter and so that said synch contacts close;

C. sensing the pulse of light, as it passes the half-open position of the shutter;

D. generating an electrical pulse equal in duration to the absolute time interval between the half-open point of the shutter and the closure of the synch contacts;

E. gating said pulse with a source of clock-timing pulses;

.and

F. measuring absolute time interval between shutter opening and synch contacts closure, as a function of passed clock-timing pulses. 

1. A method for measuring shutter speed in a camera comprising: A. supporting the camera shutter adjacent a light source; B. Activating said shutter, so that a pulse of light passes therethrough; C. sensing the duration of the light, as it passes between the half-open and half-closed positions of the shutter; D. generating a plurality of electrical clock pulses during the time between the half-open and half-closed positions of the shutter; E. counting said electrical clock pulses generated; and F. displaying speed as a function of counted pulses.
 2. A method for measuring shutter speed in a camera comprising: A. supporting the camera shutter adjacent a light source; B. activating said shutter, so that a pulse of light passes therethrough; C. sensing the duration of the pulse of light, as it passes between the half-open and half-closed positions of the shutter; D. generating an electrical pulse equal in duration to the pulse of light between the half-open and half-closed positions of the shutter; E. gating said electrical pulse with a source of clock-timing pulses; and F. measuring shutter speed as a function of said clock-timing pulses.
 3. A method for measuring shutter speed in a camera comprising: A. supporting the camera shutter adjacent a light source; B. activating said shutter, so that a pulse of light passes therethrough; C. sensing the duration of the pulse of light, as it passes between the half-open and half-closed positions of the shutter; D. generating an electrical pulse equal in duration to the pulse of light between the half-open and half-closed positions of the shutter; E. gating said pulse with a source of clock-timing pulses; F. measuring shutter speed as a function of said clock-timing pulses; and G. displaying said shutter speed as a digital readout.
 4. Method of measuring shutter speed as in claim 3, including: H. selectively varying the clock-timing rate, according to the anticipated length of the electrical pulse.
 5. Method for measuring shutter speed as in claim 4, including generating of said electrical pulse, such that said pulse swings between a negative voltage and a positive voltage of equal magnitude and has zero voltage at the half-open position of the shutter and zero voltage at the half-closed position of the shutter.
 6. Method of measuring shutter speed as in claim 5, wherein said clock-timing pulse rates are an integer power of
 10. 7. Method of measuring shutter speed as in claim 6, including displaying ''''overflow'''' when the number of counted timing pulses exceeds the capacity of the counter.
 8. Method of measuring frames per second in a motion picture camera, comprising: A. positioning a light source in the camera film gate; B. operating the camera for a period of a least 10 seconds; C. sensing the pulses of light passing through the shutter during the period of operation; D. initiating a 10-second timing cycle upon the receipt of said first pulse; E. generating electrical pulses equal in number to the pulses of light; F. gating said electrical pulses with the 10-second cycle; G. counting said electrical pulses during said 10-second cycle; and H. displaying frames per second rate of the camera as a function of counted pulses.
 9. Method of measuring absolute time interval between shutter opening and synch contacts closure in cameras comprising: A. supporting the camera shutter adjacent a light source; B. activating said shutter so that a pulse of light passes through the shutter and so that said synch contacts close; C. sensing the pulse of light, as it passes the half-open position of the shutter; D. generating an electrical pulse equal in duration to the absolute time interval between the half-open point of the shutter and the closure of the synch contacts; E. gating said pulse with a source of clock-timing pulses; and F. measuring absolute time interval between shutter opening and synch contacts closure, as a function of passed clock-timing pulses. 